The present invention relates, in general, to communication networks, and more particularly to partitioning network elements.
In a communication system having a plurality of communication nodes connected to a bus, typically all the nodes monitor the messages on the bus. Some such communication nodes may operate in a first “normal” operational mode and in second, low power mode, sometimes referred to as “sleep” mode, to reduce power consumption. While operating in the low power mode, each time a message is communicated over the bus all of the communication nodes typically must “wake up” from low power mode to process the message—even though the message may be intended for only a subset (or only one) of the communication nodes. Each time each node wakes up from the lower power mode increases the power consumption of the network. Because all of the nodes connected to the bus typically must wake up each time a message is communicated over the bus, some (or many) of the nodes may be unnecessarily waking up from sleep mode (because the messages are not intended for such communication nodes), thereby unnecessarily increasing power consumption of the network.
Accordingly, it may be desirable to have a device, system, and method for reducing the number of communication nodes that are woken up from sleep mode to process messages intended for other communication nodes to thereby consume less power.
For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, are only schematic and are non-limiting, and the same reference numbers in different figures denote the same elements, unless stated otherwise. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device that controls current flow through the device such as a gate of an MOS transistor or a base of a bipolar transistor. It will be appreciated by those skilled in the art that the words “during”, “while”, and “when” as used herein relating to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action but that there may be some small but reasonable delay, such as a propagation delay, between the reaction that is initiated by the initial action. Additionally, the term “while” means that a certain action occurs at least within some portion of a duration of the initiating action. The use of the word “approximately” or “substantially” means that a value of an element has a parameter that is expected to be close to a stated value or position. However, as is well known in the art there are always minor variances that may prevent the values or positions from being exactly as stated. It is well established in the art that variances of up to at least ten percent (10%) (and up to twenty percent (20%) for semiconductor doping concentrations) are reasonable variances from the ideal goal of exactly as described. When used in reference to a state of a signal, the term “asserted” means an active state of the signal and “negated” means an inactive state of the signal. The actual voltage value or logic state (such as a “1” or a “0”) of the signal depends on whether positive or negative logic is used. Thus, “asserted” can be either a high voltage or a high logic or a low voltage or low logic depending on whether positive or negative logic is used and “negated” may be either a low voltage or low state or a high voltage or high logic depending on whether positive or negative logic is used. Herein, a positive logic convention is used, but those skilled in the art understand that a negative logic convention could also be used. The terms “first”, “second”, “third” and the like in the Claims or/and in the Detailed Description, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of operation in other sequences than described or illustrated herein. For clarity of the drawings, doped regions of device structures may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles.
In addition, the description illustrates a cellular design (where the body regions may be a plurality of cellular regions) instead of a single body design (where the body region may be comprised of a single region formed in an elongated pattern, typically in a serpentine pattern). However, it is intended that the description is applicable to both a cellular implementation and a single base implementation.